1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly to a flash memory that can have the erasure unit block configuration modified.
2. Description of the Background Art
From the functional perspective, a flash memory is a collective erasure type non-volatile semiconductor memory device capable of electrical programming and erasure. The demand for flash memories in portable equipment and the like is great by virtue of its low cost and electrical erasure function, leading to active research and development. A flash memory employs as a memory cell a transistor including, for example, a floating gate to alter the threshold voltage (referred to as memory transistor, hereinafter).
FIG. 26 shows an array configuration of a conventional flash memory.
For the sake of simplification, a memory array of 8 M bits as a whole will be described with reference to FIG. 26. A memory array 500 includes blocks B000-B007, each block formed of memory cells corresponding to 4 k words (64 k bits), blocks B008-B022, each block formed of memory cells corresponding to 32 k words (512 k bits), and a block B100. Each of blocks B000-B022 corresponds to a basic unit of erasure operation in a flash memory.
Flash memories often require a region of 4 k words. Therefore, memory array 500 includes blocks B000-B007 having a storage capacity smaller than that of a general data storage region. Such regions of 4 k words are called, for example, xe2x80x9cboot blocksxe2x80x9d or xe2x80x9cparameter blocksxe2x80x9d.
A boot block is a region read by the CPU of a system mounted with a flash memory at the start of the system immediately after power is turned on. A parameter block is a region where data expected to be rewritten frequently is temporarily written. The block having the storage capacity of 32 k words is used as the region to store general data and programs. A flash memory must incorporate blocks differing in size depending upon the application.
Block B100 is a region equivalent to blocks B000-B007 from the address allocation perspective, and is a non-used region. Memory block B100, even though not used, has a configuration similar to that of each of blocks B008-B022 since continuity of signals on the memory array must be maintained.
The selection of a memory block is effected by block select signals BAVS0, BAVS1, and BAVM0-BAVM3 to select a block vertical position, and block select signals BAH0-BAH3 to select a block horizontal position. When a vertical block position and a horizontal block position are both rendered active, the block corresponding to a crossing thereof is selected. For example, when block B008 is to be selected, select signals BAVM0 and BAH1 are rendered conductive whereas the remaining select signals are rendered inactive.
FIG. 27 is a block diagram of a configuration of a conventional block select decoder generating a memory block select signal.
Referring to FIGS. 26 and 27, a block select decoder 502 generates block select signals BAV0, BAVS1, BAVM0-BAVM3, and BAH0-BAH3 using address bits A12-A18 of an externally applied address signal. Block select decoder 502 includes a 4-input NOR circuit 562 receiving address bits A15, A16, A17 and A18 to output a select signal BOP, a vertical block select circuit 564 providing select signals BAVS0, BAVS1, and BAVM0-BAVM3 of the vertical position in accordance with address bits A14, A17, A18 and select signal BOP, and a horizontal block select signal 566 providing select signals BAH0-BAH3 of the horizontal position in accordance with address bits A12, A13, A15 and A16 and select signal BOP.
Vertical block select circuit 564 includes an address decode unit 582 rendered active in accordance with select signal BOP to decode address bit A14 and output signals BAVS0, BAVS1, and an address decode unit 584 operating when select signal BOP is inactive and ceasing operation when select signal BOP is rendered active. Address decode unit 584 decodes address bits A17 and A18 when active to output signals BAVM0-BAVM3.
Horizontal block select circuit 566 includes an address select unit 610 providing address bits A12 and A13 as select address bits SA0, SA1 when select signal BOP is rendered active, and providing address bits A15 and A16 as select address bits SA0, SA1 when select signal BOP is inactive and an address decode unit 612 decoding select address bits SA0, SA1 to output signals BAH0-BAH3.
In the case of a memory array of 8 M bits shown in FIG. 26, the address bits selecting a 32 k-word block are A15, A16, A17 and A18 in a 1-word 16-bit structure. The address bits selecting a 4 k-word block are A12, A13 and A14. The conventional example described here is based on a configuration in which four memory blocks are disposed in the horizontal direction as shown in FIG. 26.
First, activation/inactivation of signal BOP selecting a 4 k-word region is determined by NOR circuit 562.
When an address corresponding to memory blocks B008-B022 is input, signal BOP is rendered inactive, whereby address decode unit 582 renders signals BAVS0 and BAVS1 inactive, whereas address decode unit 584 renders active one of select signals BAVM0-BAVM3 of the vertical memory blocks active in accordance with address bits A17 and A18.
In this case, address select unit 610 outputs address bits A15 and A16 as select address bits SA0 and SA1. Therefore, address decode unit 612 decodes address bits A15 and A16 to render active one of select signals BAH0-BAH3.
When all address bits A15-A18 are at an L level (logical low), select signal BOP is rendered active. This indicates that an address is input corresponding to non-used memory block B100 of FIG. 26. In this case, a corresponding region of memory blocks B000-B007 is selected instead of selecting memory block B100. Specifically, when signal BOP is rendered active, address decode unit 584 is rendered inactive, and signals BAVM0-BAVM3 are rendered inactive. Then, address decode unit 582 decodes address bit A14 to render active one of signals BAVS0 and BAVS1.
When signal BOP is active, address select unit 610 outputs address bits A12 and A13 as select address bits SA0 and SA1. Therefore, address decode unit 512 decodes address bits A12 and A13 to render active one of signals BAH0-BAH3.
Conventionally, the block division and address allocation determined by block select decoder 502 are always fixed. In other words, the region of 8 M bits was handled as eight blocks of a 4 k-word block and fifteen blocks of a 32 k-word block B008-B022, i.e., a total of 23 blocks.
Thus, memory array 500 of FIG. 26 includes 23 blocks of memory blocks B000-B022 to be used. This means that an erasure operation must be designated from outside the chip 23 times in order to erase the entire memory array of 8 M bits.
In FIG. 26 the eight blocks of 4 k word blocks, i.e. blocks B000-B007, are allocated the least significant side of the address. This is termed a xe2x80x9cbottom boot typexe2x80x9d. However, there is a case where a top boot type flash memory having the blocks of 4 k words allocated the most significant side of the address is required, depending upon the system employed. In order to modify a bottom boot type memory into a top boot type memory for usage, the conventional approach was to invert a particular address bit in an address input buffer.
FIG. 28 is a circuit diagram showing a configuration of such a conventional address input buffer 516.
Referring to FIG. 28, address input buffer 516 includes address inversion circuits 520, 522 and 524 switching the non-inversion/inversion of address bits A15, A16 and A17 in accordance with a signal TOP rendered active when the memory is switched to a top boot type memory for usage.
Address inversion circuit 520 includes an inverter receiving and inverting an externally applied address bit ext.A15, an inverter 528 receiving and inverting signal TOP, a NAND circuit 530 receiving an output of inverter 526 and signal TOP, a NAND circuit 532 receiving address bit ext.A15 and an output of inverter 528, and a NAND circuit 534 receiving outputs of NAND circuits 530 and 532 to output address bit A15.
Address inversion circuit 522 has an internal configuration similar to that of address inversion circuit 520, provided that an address bit ext.A16 is input and an address bit Al6 is output. Therefore, the internal configuration of address inversion circuit 522 will not be described. Address inversion circuit 524 has an internal configuration similar to that of address inversion circuit 520, provided that an address bit ext.A17 and is input and an address bit A17 is output. Therefore, the internal configuration of address inversion circuit 524 will not be described.
FIG. 29 shows an array configuration of another conventional flash memory.
Referring to FIG. 29, each of blocks B000-B015 is formed of memory cells corresponding to 32 k words (512 k bits). Memory array 700 is absent of a memory block formed of memory cells corresponding to 4 k words. Memory block 700 is an 8 Mbit region entirely configured with 16 blocks formed of memory cells corresponding to 32 k words. In contrast to memory array 500 of FIG. 26 requiring an erasure operation of 23 times to erase the 8 Mbit region, memory array 700 requires an erasure operation of 16 times for the erasure of the 8 Mbit region.
A prior art document related to block erasure is disclosed in, for example, Japanese Patent Laying-Open No. 2002-133877.
Conventionally, the block division and address allocation to each block were always fixed. Therefore, in a flash memory product of 8 M bits described with reference to FIG. 26, for example, there are a total of 23 blocks in accordance with a specification including blocks of 4 k words, i.e., 8 of 4 k word blocks and 15 of 32 k word blocks.
In a flash memory product absent of a 4 k-word block described with reference to FIG. 29, 16 of 32 k word blocks constitute 8 M bits. In other words, designing and fabrication of a memory device must be carried out as completely different products depending upon the absence/presence of a block of 4 k words.
Reflecting the increase of the storage capacity of a flash memory, a chip having a boot block of 4 k word blocks both at the least significant bit side and most significant bit side of the address has been developed in addition to those of the least significant bit side or the most significant bit side address allocation. Such a chip is referred to as a xe2x80x9cdual boot type chipxe2x80x9d. In the case where two of the dual boot type chips are to be combined for usage as a large memory region, there is a disadvantage that the usability is degraded since blocks of 4 k words are present intermittently at the center of the address region.
In view of the foregoing, an object of the present invention is to implement simultaneously by one chip a flash memory with a 4 k-word block and a flash memory without a 4 k-word block, in a flash memory divided into a plurality of erasure blocks including a block of a small storage capacity such as a boot block, and simplify the design and fabrication thereof.
According to an aspect of the present invention, a non-volatile semiconductor memory device includes a first basic memory block, a plurality of second basic memory blocks, and an erasure control circuit. The first basic memory block has a plurality of memory cells arranged in a matrix. The first basic memory block has a first storage capacity corresponding to a unit of collective erasure. The collective erasure is not allowed in a partial region of the first basic memory block. The partial region of the first basic memory block has a second storage capacity smaller than the first storage capacity. The plurality of second basic memory blocks are provided independent of the first basic memory block. Each of the plurality of second basic memory blocks has a plurality of memory cells arranged in a matrix. Each of the plurality of second basic memory blocks has the second storage capacity. The total storage capacity of the plurality of second basic memory blocks is equal to the first storage capacity. The erasure control circuit switches, in accordance with a select signal, between a first operation of erasing one of the plurality of second basic memory blocks in accordance with an erasure command and a second operation of erasing the plurality of second basic memory blocks collectively in accordance with the erasure command.
According to another aspect of the present invention, a non-volatile semiconductor memory device includes a first basic memory block, a plurality of second basic memory blocks, and an erasure control circuit. The first basic memory block has a plurality of memory cells arranged in a matrix. The first basic memory block has a first storage capacity corresponding to a unit of collective erasure. The collective erasure is not allowed in a partial region of the first basic memory block. The partial regionof the first basic memory block has a second storage capacity smaller than the first storage capacity. The plurality of second basic memory blocks are provided independent of the first basic memory block. Each of the plurality of second basic memory blocks has a plurality of memory cells arranged in a matrix. Each of the plurality of second basic memory blocks has the second storage capacity. The total storage capacity of the plurality of second basic memory blocks is equal to the first storage capacity. The erasure control circuit switches, in accordance with a switch signal, between a first operation of erasing one of the plurality of second basic memory blocks in accordance with an erasure command and a second operation of erasing the first basic memory block in accordance with the erasure command.
According to the present invention, a plurality of types of non-volatile semiconductor devices can be implemented, one type of non-volatile semiconductor memory device having each small block corresponding to the erasure unit and one type of non-volatile semiconductor memory device having all the small blocks collectively corresponding to an erasure unit by modifying the manner of applying a switch signal. The non-volatile semiconductor device of the present invention is advantageous in that the cost for developing a plurality of types and the cost of controlling fabrication can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.